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[VHDL-FPGA-Verilog] Orthogonization_Module

Description: 接收机数字部分正交混频模块‘ 包括verilog代码 matlab仿真 word文档 testbench代码(Receiver digital part orthogonal frequency mixing module ' Including Verilog code Matlab simulation Testbench code)
Platform: | Size: 1798144 | Author: nokkk | Hits:

[VHDL-FPGA-Verilog] CIC_Filter_Module

Description: 数字接收机cic抽取模块 抽取倍数可以选择 包括verilog代码 word文档 matlab仿真 testbench代码(CIC decimation module of digital receiver Extraction multiple can be selected Including Verilog code Word document Matlab simulation Testbench code)
Platform: | Size: 3013632 | Author: nokkk | Hits:

[Other] AHB RAM

Description: Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
Platform: | Size: 21811200 | Author: 容止 | Hits:

[3G develop] RS纠错码的实现

Description: RS纠错码的编码实现verilog语言 可以运行，并包含testbench，可以进行测试 适用于初学者
Platform: | Size: 5142 | Author: 1228721125 | Hits:
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